The present invention provides techniques for forming test structures in die on semiconductor wafers, and more specifically, to techniques for interleaving test structures of adjacent die that can be removed during high volume production using the same reticle.
In semiconductor processing, die are formed on semiconductor wafers using a reticle. A reticle is a transparent substrate, such as quartz, that is placed in the near focal plane of a projection system. Radiation, such as ultra violet light, is passed through the reticle and is projected onto a wafer to transfer the image upon that wafer. A patterned opaque coating is formed on the reticle, to define the image to be projected. The image consists of one or more die and various test and measurement structures between and around the die.
The area of the wafer that is exposed to radiation through an opening in the opaque coating of the reticle is referred to as the field area. One or more die can be patterned in a single field area. Multiple field areas can be formed next to each other by moving the reticle across the wafer.
An additional masking layer referred to as a blade, or blades, also masks the formation of the die. Because the opaque coating often contains spurious pinholes and defects, the blade is used to prevent imperfections in the opaque coating from forming spurious patterns on the wafer. However, alignment of the blade to the edge of the die is typically poor, because of mechanical tolerances, and because the blade is out of the focal plane.
Each die includes a primary die area that is patterned according to an integrated circuit design. Each die also includes test structures. Test structures are typically formed on a wafer in thin vertical and horizontal scribelines situated between adjacent primary die. The test structures include some or all of the processing layers used to form the integrated circuit.
The test structures can be used for many purposes. For example, the test structures can be used to measure the accuracy of the pattern transfer process, by providing a predefined structure with a physical dimension that can be measured. As another example, several layers can be combined to produce a simple semiconductor device or circuit, which can be electrically measured. The test structures are formed in narrow sacrificial regions that separate the die from each other. After the tests are performed, the test structures are cut out of the wafer and discarded.
With each new generation of semiconductor processing technology, the maximum field area exposed by a reticle increases. By increasing the field area of a reticle, less exposures are needed to pattern an entire wafer, saving time and cost. Therefore, the largest possible field area is typically used for each exposure, and each field is filled with as many die as possible.
Some integrated circuits require a large die area. In some cases, only one die is formed within a single reticle field area. As the reticle field area increases, the die area increases by the square of the diameter of the field size. However, in processes that place only one die in each reticle field area, the length of each scribeline only increases linearly as the reticle field area increases. Thus, for single-die field areas, the scribeline test structures become an increasingly smaller percentage of the total field area.
Some types of integrated circuits require complex processing technologies with many process layers. These types of circuits often need to have a larger test structure area relative to the size of the die in order to be able to perform all of the tests needed to verify numerous aspects of a complex processing technology. In addition, during the development of a new Silicon process technology, and verification of a new integrated circuit product, it is also advantageous to perform additional tests. These tests are used to monitor and refine the process. They are also used to better understand the interaction of the process with the integrated circuit design. If integrated circuits with complex processing technologies and many layers are formed in a single-die field area, the scribeline test structure area is often too small to accommodate all of the tests that need to be performed.
One solution is to create larger test structures relative to the primary die in each reticle field area. The area of the test structures can be increased by increasing the width of the vertical and horizontal scribelines. This means that a larger fraction of the area of a wafer is used to produce test structures, and a smaller fraction of the wafer is used to produce usable product. Specifically, the die is created so that enough test structure area exists in each die to perform the required tests. However, the cost of producing the product is increased.
Once the tests have been performed and proper operation of the test chip is verified, there is no longer a need for large scribelines between the die. It is more desirable to have narrower scribelines between the die for high volume production, so that more die can be formed on each wafer, and less sacrificial area is consumed by the test structures.
Another solution would be to produce a dedicated test chip. This die would include only test structures without a primary die. Producing the test chip may also require designing a dedicated reticle set. There is no usable or salable product. The cost of generating a dedicated test chip is expensive and the cost increases dramatically with each new generation of semiconductor processing technology. After the test chip experiments are completed, the data obtained by measuring the test chips are no longer required.
Therefore, it would be desirable to provide techniques for forming die on semiconductor wafers that create larger sacrificial test structures between the die to allow testing of complex processing technologies with many layers. It would also be desirable to provide techniques that allow the size of the test structures to be reduced during high volume die production without having to redesign the process steps or redesign the processing equipment.